Switching power converters are widely used due to their high efficiency and simple internal structure. Many control modes could be used to control switching power converters, such as constant on time control mode, peak current control mode, and average current control mode. Among these control modes, constant on time control mode is getting more and more popular per its fast transient response, simple structure and smooth switch of operation mode.
FIG. 1 schematically illustrates a conventional constant on time converter 100. The constant on time converter 100 comprises an on time control circuit 101, a comparing circuit 102, a logic circuit 103 and a switching circuit 104. Switching circuit 104 comprises a power switch. The switching circuit 104 is configured to provide an output voltage VOUT from an input voltage VIN via turning the power switch ON and OFF. The on time control circuit 101 is configured to provide an on time period control signal COT to control an on time period of the power switch. The comparing circuit 102 comprises an output terminal configured to provide a comparing signal SET via comparing the output voltage VOUT with a reference signal VREF. The logic circuit 103 comprises a first input terminal coupled to the output terminal of the comparing circuit 102 to receive the comparing signal SET, a second input terminal coupled to the on time control circuit 101 to receive the on time period control signal COT, and an output terminal coupled to a control terminal of the power switch to provide a control signal CTRL.
When an equivalent series resistance (ESR) of an output capacitor in the switching circuit 104 is small, a sub-harmonic oscillation may occur at output voltage VOUT, and constant on time converter 100 may be unstable. A slope compensation circuit 105 may be employed to avoid the sub-harmonic oscillation. The slope compensation circuit 105 comprises an output terminal configured to provide a slope compensation signal VSLOPE. The comparing circuit 102 is configured to provide the comparing signal SET via comparing a sum of the slope compensation signal VSLOPE and the output voltage VOUT with the reference signal VREF.
To ensure that the switching converter 100 is maintained stable under different status, the slope of the slope compensation signal VSLOPE should be sufficiently large, e.g. greater than a critical value that may be determined by a switching frequency, a duty cycle and an output capacitor. As a result, transient response of the converter 100 would be degenerated if the slope of the slope compensation signal VSLOPE is too high. Worse, when the input voltage VIN or a load current IOUT changes, the output voltage VOUT would also be changed if the slope of the slope compensation signal VSLOPE is maintained constant, so as to affect line regulation of the switching converter 100 that indicates the stability of output voltage versus input voltage, or load regulation of the switching converter 100 that indicates the stability of output voltage versus load current. So, it is very important to design slope compensation circuits to adjust the slope of the slope compensation signal VSLOPE. The slope may be adjusted according to one or more following factors: switching frequency of the power switch; duty cycle of the power switch; output capacitors; the input voltage VIN; output voltage VOUT; and the load current IOUT.